1. Field of Invention
This invention is in the field of semiconductor manufacturing and, more specifically, enabling electrical measurements via nanoprobing at wafer level process monitoring to accomplish in-line monitoring, defect review and process control.
2. Related Art
Process engineers always tried to get as much information as possible about devices and circuits they built. Device information can be divided into two groups: physical and electrical characteristics. Electrical characteristics give the ultimate properties of the fabricated device and, if these conform to the design, nothing else is really needed for process monitoring and control. Certainly, electrical characteristics would be sufficient if a process never breaks or drifts over time. However, when the process does break or drift and factory yield goes down, process engineers need to perform failure analysis (FA) to investigate the failure and find out what process failed. At this point physical characteristics (such as critical dimensions (CD), film thickness and uniformity, chemical composition, interfaces, etc.) suddenly become important to know. Process engineers need to investigate at what specific step the process failed. Physical modeling of the devices is often used in order to understand the dependence of electrical properties on the device's physical parameters and process tolerances. This classical approach worked well for many years. Recently; however, this approach began failing and, due to increasing fabrication complexity, the approach's failure rate is predicted to increase.
In current and future chips, internal device and atomic dimensions become comparable. This means that surfaces and interfaces have significant impact on device properties. Bulk material models do not describe well dependencies of device electrical properties on dimensions, material composition (doping, Si oxynitride, Hf oxide, etc.) and physical characteristics. In addition, accuracy of dimensional metrology and physical characterization is also degrading. As a result, yield and process engineers confront a new challenge of finding a root cause of failure with less and less physical and dimensional information available for them.
To resolve this problem engineers have to use increasingly more electrical characteristics of the devices themselves. Unfortunately, the electrical data become available only when at least one level of interconnect is formed. In most cases, critical elements of circuitry may be tested only after several layers of interconnects are built. This takes time and resources, and often causes scrap of many expensive wafers.
Presently, no front-end in-line process monitoring is electrical. Virtually all electrical measurements are made at least after the first metal is fully fabricated (i.e., during back end fabrication). This is too late in the process as by that stage all of the processing required to fabricate the functional devices of the chip (i.e., transistors, memory cells, etc., generally referred to as front end) have been completed. If a problem occurred during the front end fabrication steps and was not detected during that time, many wafers are scrapped. The earlier the problem is found, the less loss is expected. The present front end monitoring tools often find defects which do not affect electrical performance and, otherwise, miss defects which do impact performance. Those that completely “kill” a device are called “killer defects.” As a rule, they are only discovered after the IC is fully fabricated and tested electrically. The defective IC undergoes fault isolation and nanoprobing before the “killer” can be identified in physical failure analysis (PFA). Many of these “killer” and performance defects would be discovered early-on if electrical measurements were made early in the process flow. Therefore, electrical nanoprobing conducted systematically and early in the flow could catch (new) “killer” defects early and prevent wafer scrap.
In practice, electrical tests are performed using specially designed test structures, wherein almost all electrical test structures are located in scribe line because IC real estate is very expensive, especially on production chips. However, it is known to artisans in the field that electrical properties of devices depend on specific layout (micro loading effects) and also vary across die/chip (macro loading effects). The test structures, being on the scribe lines and not the actual chip, do not properly reflect the electrical performance of the actual devices within the chip. Therefore, intra-chip distribution of electrical properties of transistors from the impact of micro and macro loading effects on electrical characteristics are simply unknown.
In order to electrically test a circuit, a prober must physically contact the elements of the device within the IC. However, contact and scanning probers, such as atomic force probers (AFP) require contact and imaging force that exceeds the so-called “non-contact” force “accepted” by fabs (a few nanoNewtons or nN). Various proposals have been made in the past for ways to electrically characterize devices and critical circuits early in the process flow and even step by step through the flow. Examples of possible solution can be found in U.S. Pat. Nos. 5,899,703 and 6,399,400.
According to one proposal, a sacrificial layer of dielectric is deposited at the layer of interest. New specially designed pattern—which is different from the actual circuitry of the chip—is used to open via (or other conducting elements) of interest. The patterning can be done by optical lithography or using direct writing by e-beam or laser beam. The etching of dielectric, deposition of metal followed by polishing form sacrificial circuits used to test devices and circuits of interest. According to the authors, once testing is done the top metal and dielectric layers can be removed by etching and polishing and the standard flow can be continued.
According to another proposal, a specific case of fabrication of integral circuits (IC) using a so-called gate array IC wafer is envisioned. The authors suggest to stop at interconnect level at which speed of devices and circuits can be tested. The wafers then are sorted according to the obtained data on speed of their devices. The speed grading circuits are located on die or in scribe line. Customization of gate array IC wafer is done after test using remaining available layers of interconnect. The purpose of this proposal is to sort ‘slow’, ‘medium’, and ‘fast’ IC's prior to completion of fabrication.
In both examples U.S. Pat. Nos. 5,899,703 and 6,399,400 sacrificial layers (the top or the bottom ones) are used to do early electrical diagnostics of wafers and individual chips. In both cases it requires additional wafer processing including expensive high-resolution patterning of the top or bottom layers. The additional processing and de-processing of wafers increase the risk of misprocessing and wafer scrap. In both cases placement of large test structures (standard test structure has 40 contact pads, each one of them with dimensions 50×50 um2 or more) is limited by high cost of wafer and chip real estate. For instance, it is difficult to imagine placement of several test structure across chip e.g., to test macro-loading effects. Also use of standard electrical test structures is limiting investigation of micro-loading effects since test structures have specific layout. Both approaches are too complex or/and risky to try to implement them step by step through process flow. In other words, these methods can be used occasionally and most likely off-line to solve complex monitoring problems but it is very hard to imagine that these methods will be used routinely, in-line for process monitoring and control. This is just impractical.
Several nanoprobes capable of electrical testing of individual transistors and critical circuits have been developed. Modern nanoprobes are capable of electrical testing of individual devices (transistors, diodes, etc.) and circuits of a single chip, and are most commonly used for failure analysis. These tools operate on single chips, not on wafer-size samples. AFM-based nanoprobe have also been used for non-destructive in-line electrical probing of chips at post-contact chemical-mechanical polishing (CMP) process step. Unfortunately, implementation of in-line AFP for wafer-size samples has several significant obstacles, some examples are as follows.
(1) Sample and probe damage caused by high probe force necessary for establishing low resistance probe-sample contact:
                Particle generation and wafer contamination,        IC contact damage (smearing),        Poor AFP spatial resolution caused by damaged dull probes.(2) Wafer modification and deviation from the standard process flow:        Interlayer dielectric etching required to reveal contact's location from the metal/dielectric topography (contacts can't be found using AFM on most post CMP samples),        Metal oxide removal and cleaning process steps are required prior AFP (contact corrosion is caused by reaction of metal with CMP slurry or/and atmospheric gases).        
As a result, to date no wafer level in-line nanoprobing device has been developed. Instead, new methods, including off-line nanoprobing, are used today to replace classical process control schemes. These expensive off-line techniques are used today for technology development, ramp up and even manufacturing control. This change impacts cost of technology development and manufacturing and also contributes to a systematic reduction of yield observed for the latest technologies.
No SEM-based in-line wafer level AFM or nanoprobe is known today. Several versions of off-line SEM-based AFM's and nanoprobes are known, which may be used to test chips. Carl Zeiss' Merlin SEM can be combined with AFM and optical microscope. Details can be found in the “MERLIN series” brochure by Carl Zeiss. The 3TB 4000 system is a combined AFM, FIB and SEM by Nanonics Imaging Ltd. This AFM uses laser-free tuning fork force sensor. Other examples of SEM and AFM hybrid tools are Attocube Systems AG (www.attocube.com), and Nanosurf AG (www.nanosurf.com), Kleindiek Nanotechnik GmbH (www.kleidiek.com). A system having nanoprobes and charged particle beam device used for testing individual chips or devices (DUT) is disclosed in, for example, U.S. Pat. Nos. 7,285,778, 7,319,336, 7,675,300 and 8,536,526. These systems; however, cannot be used to test chips within wafers and cannot be used in-line. Research oriented off-line SEM- and FIB-based nanoprobes have been designed by Kleindiek Nanotechnik GmbH. The next level of SEM-based nanoprobing is provided by DCG Systems, Inc. The latest model nProber II is an off-line SEM-based automated nanoprobe with 12.5×12.5 mm2 load-locked sample, eight low drift probes and overall capability suitable for 10 nm technology.